The so-called "chip scale package" is referred to the post-package chip module which is nearly corresponding in size to the semiconductor chip, thereby resulting in the reduction in overall volume of an electronic terminal product made of the chip module.
FIG. 1 shows a sectional schematic view of a conventional semiconductor chip module, which conforms to the requirements of the chip scale package and comprises a double-sided conductive base 10; a semiconductor chip 12 attached to the upper surface of the base 10 by an adhesive layer 14 such that the active surface of the chip faces upward; a plurality of bonding wires 15 connecting a plurality of bonding pads (not shown in the drawing) disposed on the active surface of the chip 12 with the electrical bonding points (not shown in the drawing) which are disposed on the upper surface of the base 10; a plurality of spherical points grid arrays 16 disposed in the underside of the base 10; and a plastic packaging unit 18 for containing hermetically the chip 12 and the bonding wires 15.
Such a conventional semiconductor chip module as described above is defective in design in that the double-sided base 10 must be additionally treated with the costly processes, such as drilling, electroplating, hole-filling, planarizing, etc. In addition, the total useable area of the base 10 is substantially reduced by the holes, which also adversely affect the layout of the printed circuit.
The U.S. Pat. No. 5,811,879 discloses a semiconductor chip module comprising a single-sided conductive base, which is free from the deficiencies of the double-sided conductive base described above. However, the single-sided conductive base is provided in the upper surface with a plurality of recesses in which the chips are secured in place by an adhesive. It is conceivable that the recesses undermine the structural integrity and strength of the single-sided conductive base. In addition, it is time-consuming to provide the chips with an adhesive coating. Moreover, the reliability of the semiconductor chip module is reduced by the interstices which exist between the recess and the chip in the event that the recess and the chip do not match well in size. In other words, such a prior art single-sided conductive base as described above has a high rejection rate.